Apple Xserve G5 Especificações Página 12
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Additional Features
A high-speed bus architecture between the memory controller and device
I/O. For more information, see “HyperTransport Technology” (page 25).
Hyper Transport
64-bit processor interface bus running at half the speed of the system
microprocessor. See “Processor Bus” (page 24).
Processor system bus
Internal 512 KB level 2 cache per processor. See “Cache Memory” (page
23).
Memory caches
ROM-in-RAM implementation with 2 MB of boot ROM. For information
about the ROM, see “Boot ROM” (page 27). For information about the
ROM-in-RAM implementation, see the references listed in “ROM-in-RAM
Architecture” (page 46).
ROM
Up to three drive bays for serial ATA (SATA) drives with independent
buses and support for hot-pluggable drives using Apple Drive Modules.
See “Hard Disk Drives” (page 38).
Hard disk drive bays
Two USB 2.0 ports. See “USB Ports” (page 31).
USB 2.0 ports
Dual Ethernet ports for 10Base-T, 100Base-T, or 1000Base-T operation. See
“Ethernet Ports” (page 35).
Ethernet
Two FireWire 800 ports on back panel and one FireWire 400 on front. See
“FireWire Ports” (page 32).
FireWire por ts
Two PCI-X expansion slots for PCI or PCI-X cards. See “PCI or PCI-X
Expansion Slots” (page 25).
PCI-X card expansion
slots
The system monitors the fan speeds and reports if speeds are outside
acceptable range, indicating that a fan needs service.
System Monitoring
Table 1-2 Hardware Features of the Cluster Node Xserve G5
New Features
Dual 2.3 GHz PowerPC G5 microprocessors. See “PowerPC G5
Microprocessor” (page 23).
Microprocessor speed
Eight slots (four pairs of two) for 184-pin DIMMs (dual inline memory
modules) using ECC (error correcting code) DDR400 (double data rate)
dynamic RAM devices. Supports a maximum of 8 GB. See “RAM
Expansion” (page 41).
RAM
Additional Features
Internal 512 KB level 2 cache per processor. See “Cache Memory” (page
23).
Memory caches
64-bit processor interface bus running at half the speed of the system
microprocessor. See “Processor Bus” (page 24).
Processor system bus
12
Hardware Features
2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.
CHAPTER 1
Overview of the Xserve G5
- Xserve G5 Developer Note 1
- Contents 3
- Input and Output Devices 31 4
- Expansion 41 4
- Index 55 5
- CONTENTS 6
- Figures and Tables 7
- FIGURES AND TABLES 8
- Organization of This Document 10
- Overview of the Xserve G5 11
- CHAPTER 1 12
- Features of the Enclosure 13
- System Software 16
- Security Features 17
- Storage Support 17
- Management Support 18
- Velocity Engine Acceleration 19
- Architecture 21
- CHAPTER 2 22
- Processor Module 23
- Dual Processors 24
- Processor Bus 24
- Main Memory Bus 24
- HyperTransport Technology 25
- K2 I/O Controller 26
- Internal PCI Bus 27
- Serial ATA Interface 27
- Serial Interface 27
- Ultra DMA ATA/100 Interface 27
- FireWire Controllers 28
- Power Controller 28
- Dual System Monitor ICs 28
- System Activity Lights 28
- Device Identification 28
- Optional Graphics Card 29
- Input and Output Devices 31
- FireWire Ports 32
- FireWire 800 Connector 33
- FireWire 400 Connector 34
- Ethernet Ports 35
- Serial Port 36
- Disk Drives 37
- SuperDrive (Optional) 38
- Hard Disk Drives 38
- VGA Connector 39
- DescriptionSignal namePin 40
- CHAPTER 3 40
- Expansion 41
- DIMM Configurations 42
- RAM Addressing 42
- PCI and PCI-X Expansion Slots 43
- Apple Technical Notes 45
- PowerPC G5 Microprocessor 45
- Velocity Engine (AltiVec) 45
- Mac OS X and Mac OS Server 46
- ROM-in-RAM Architecture 46
- Open Firmware 46
- RAM Expansion Modules 47
- ATA Devices 47
- Ethernet 47
- Serial ATA 48
- USB Interface 48
- FireWire Interface 48
- EIA Rack Standards 48
- Serial Interface Standards 49
- Conventions and Abbreviations 51
- APPENDIX B 52
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