Apple Xserve G5 Especificações descarregar pdf (Página 21)

This chapter describes the architecture of the Xserve G5. It includes information about the major

components on the logic boards: the microprocessor, the other main ICs, and the buses that connect

them to each other and to the I/O interfaces.

Block Diagram and Buses

The architecture of Xserve G5 is based on one or two PowerPC G5 microprocessors and two custom

ICs: the U3H memory controller and bus bridge and the K2 I/O controller. Figure 2-1 (page 22) is a

simplified block diagram of a standard Xserve G5 with two PowerPC G5 microprocessors. The single

microprocessor configuration and the cluster node configuration have similar structure with fewer

features, as identified in Table 1-1 (page 11) and Table 1-2 (page 12) and throughout this developer

note.

Block Diagram and Buses 21

CHAPTER 2

Architecture

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Apple Xserve G5 Especificações Página 21